View ATA6631-14_8028760.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

9165f-auto-10/14 features supply voltage up to 40v operating voltage v s = 5v to 27v typically 10a supply current during sleep mode typically 35a supply current in silent mode linear low -drop voltage regulator, 85ma current capability: normal, fail-safe, and silent mode atmel ata6629: v cc = 3.3v 2% atmel ata6631: v cc = 5.0v 2% sleep mode: v cc is switched off v cc undervoltage detection with reset open drain output nres (4ms reset time) voltage regulator is short-circui t and over-temperature protected lin physical layer according to lin 2.0, 2.1 and saej2602-2 wake-up capability via lin bus (90s dominant) txd time-out timer bus pin is overtemperature and short-ci rcuit protected versus gnd and battery advanced emc and esd performance fulfills the oem ?hardware requirements for lin in automotive applications rev.1.1? interference and damage protection according to iso7637 package: s o8 ata6629/ata6631 lin bus transceiver with i ntegrated voltage regulator datasheet
ata6629/ata6631 [datasheet] 9165f?auto?10/14 2 1. description atmel ? ata6629/ata6631 is a fully integrated lin transceiver, designed according to the lin specification 2.0, 2.1 and saej2602-2, with a low-drop voltage regulator (3.3v/5v/85ma). the combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in lin bus systems. ata6629/ata6631 is designed to handle the low-speed data communication in vehicles (for exam ple, in convenience electronics). improved slope control at the lin driver ensures secure data communication up to 20kba ud. the bus output is designed to withstand high voltage. sleep mode and silent mode guarantee minimized current consumpt ion even in the case of a floating or a short circuited lin-bus. figure 1-1. block diagram 3 gnd 2 en 6 txd 5 rxd vcc 8 nres 7 short-circuit and overtemperature protection normal/silent/ fail-safe mode 3.3v/5v control unit normal and fail-safe mode rf-filter lin vs 1 4 txd time-out timer slew rate control undervoltage reset sleep mode vcc switched off wake-up bus timer atmel ata6629/ata6631 receiver v cc - + v cc 5k
3 ata6629/ata6631 [datasheet] 9165f?auto?10/14 2. pin configuration figure 2-1. pinning so8 table 2-1. pin description pin symbol function 1 vs battery supply 2 en enables normal mode if the input is high 3 gnd ground, heat sink 4 lin lin bus line input/output 5 rxd receive data output 6 txd transmit data input 7 nres output undervoltage reset, low at reset 8 vcc output voltage regulator 3.3v/5v/50ma vcc 3 4 2 1 txd nres rxd vs 8 7 6 5 gnd en lin
ata6629/ata6631 [datasheet] 9165f?auto?10/14 4 3. functional description 3.1 physical layer compatibility since the lin physical layer is independent from higher lin layers (e.g., lin prot ocol layer), all nodes with a lin physical layer according to revision 2.x can be mixed with lin physical layer nodes, which are according to older versions (i.e., lin 1.0, lin 1.1, lin 1. 2, lin 1.3) without any restrictions. 3.2 supply pin (vs) lin operating voltage is v s = 5v to 27v. an undervoltage detection is im plemented to disable transmission if v s falls below 5v, in order to avoid false bus messages. after switching on v s , the ic starts with the fail- safe mode and the voltage regulator is switched on. the supply current in sleep mode is typically 10a and 35a in silent mode. 3.3 ground pin (gnd) the ic does not affect the lin bus in the event of gnd disconnection. it is able to handle a ground shift up to 11.5% of v s . 3.4 voltage regulator output pin (vcc) the internal 3.3v/5v voltage regulator is capable of driving lo ads up to 85ma, supplying the microcontroller and other ics on the pcb and is protected against overload by means of current limitation and overte mperature shut-down. furthermore, the output voltage is monitored and will cause a reset signal at the nres output pin if it drops below a defined threshold v thun . 3.5 undervoltage reset output (nres) if the v cc voltage falls below the undervoltage detection threshold v thun , nres switches to low after tres_f ( figure 6-1 on page 15 ). even if v cc = 0v the nres stays low, because it is internally driven from the v s voltage. if v s voltage ramps down, nres stays low until v s < 1.5v and then becomes highly resistant. the implemented undervoltage delay keeps nres low for t reset = 4ms after v cc reaches its nominal value. 3.6 bus pin (lin) a low-side driver with internal current lim itation and thermal shutdown as well as an internal pull-up resistor according to li n specification 2.x is implemented. the volt age range is from ?27v to +40v. this pin exhibits no reverse current from the lin bus to v s , even in the event of a gnd shift or v batt disconnection. the lin receiver th resholds are compatible with the lin protocol specification. the fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. 3.7 input/output (txd) in normal mode the txd pin is the microcontroller interface to control the state of the lin ou tput. txd must be pulled to ground in order to drive the lin bus low. if txd is high or un connected (internal pull-up resist or), the lin output transistor is turned off and the bus is in the recessive state. during fail-safe mode, this pin is used as output and is signalling the fail- safe source. 3.8 dominant time-out function (txd) the txd input has an internal pull-up resistor. an internal ti mer prevents the bus line from be ing driven permanently in the dominant state. if txd is fo rced to low longer than t dom > 27ms, the lin bus driver is sw itched to the recessive state. nevertheless, when switching to sleep mode, th e actual level at the txd pin is relevant. to reactivate the lin bus driv er, switch txd to high (> 10s).
5 ata6629/ata6631 [datasheet] 9165f?auto?10/14 3.9 output pin (rxd) this pin reports the state of the lin bus to the microcontroller. lin high (re cessive state) is reported by a high level at rxd ; lin low (dominant state) is reported by a low level at rxd. the output has an internal pull-up resistor with typically 5k to v cc . the ac characteristics are measured wi th an external load capacitor of 20pf. the output is short-ci rcuit protected. in u npowered mode (that is, v s = 0v), rxd is switched off. 3.10 enable input pin (en) the enable input pin controls the operation mode of the device. if en is high, the circuit is in normal mode, with transmission paths from txd to lin and from lin to rxd both active. t he vcc voltage regulator operat es with 3.3v/5v/85ma output capability. if en is switched to low while txd is still high, the device is forced to silent mode. no data tr ansmission is then possible, a nd the current consumptio n is reduced to i vs typ. 35a. the vcc regulator has its full functionality. if en is switched to low while txd is low, the device is fo rced to sleep mode. no data transmission is possible, and the voltage regulator is switched off.
ata6629/ata6631 [datasheet] 9165f?auto?10/14 6 4. modes of operation figure 4-1. modes of operation 4.1 normal mode this is the normal transmitting and receiving mode of the li n interface, in accordance with lin specification 2.x. the v cc voltage regulator operates with a 3.3v/5v output voltage, with a low tolerance of 2% and a maximum output current of 85ma. if an undervoltage condition occurs, nres is switched to low and the ic changes its state to fail-safe mode. table 4-1. modes of operation modes of operation transceiver v cc lin fail safe off 3.3v/5v recessive normal on 3.3v/5v txd depending silent off 3.3v/5v recessive sleep off 0v recessive unpowered mode (see section 4.5) a: v s > vs thf b: v s < vs thu c: bus wake-up event d: nres switches to low fail-safe mode normal mode vcc: 3.3v/5v with undervoltage monitoring communication: on vcc: 3.3v/5v with undervoltage monitoring communication: off silent mode vcc: 3.3v/5v with undervoltage monitoring communication: off sleep mode vcc: switched off communication: off go to silent command a txd = 0 en = 0 txd = 1 en = 0 en = 1 en = 1 en = 1 b b b c or d d or c b local wake-up event go to sleep command
7 ata6629/ata6631 [datasheet] 9165f?auto?10/14 4.2 silent mode a falling edge at en while txd is high switches the ic into si lent mode. the txd signal has to be logic high during the mode select window ( figure 4-3 on page 8 ). the transmission path is disabled in sil ent mode. the overall supply current from v batt is a combination of the i vssilent = 35a plus the v cc regulator output current i vcc . figure 4-2. switch to silent mode in silent mode the internal slave termination between pin lin a nd pin vs is disabled to minimize the current consumption in case pin lin is short-circuited to gnd. only a weak pull-up current (typically 10a) between pin lin and pin vs is present. the silent mode can be activated independent ly from the current level on pin lin. if an undervoltage condition occurs, nr es is switched to low and the atmel ? ata6629/ata6631 changes its state to fail-safe mode. a voltage less than the lin pre-wake detection v linl at pin lin activates the internal lin receiver and st arts the wake-up detection timer. delay time silent mode t d _sleep = maximum 20s mode select window lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en normal mode silent mode
ata6629/ata6631 [datasheet] 9165f?auto?10/14 8 a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (> t bus ) and the following rising edge at pin lin (see figure 4-3 ) results in a remote wake-up request which is only possible if txd is high. the device switches from silent mode to fail-safe mode, then the internal lin slave terminat ion resistor is switched on. the remote wake-up request is indicated by a low level at pi n rxd and txd to interrupt the microcontroller ( figure 4-3 ). en high can be used to switch directly to normal mode. figure 4-3. lin wake-up waveform diagram from silent mode undervoltage detection active silent mode 3.3v/5v fail-safe mode 3.3v/5v normal mode low fail-safe mode normal mode en high high nres en vcc rxd lin bus bus wake-up filtering time t bus high high txd
9 ata6629/ata6631 [datasheet] 9165f?auto?10/14 4.3 sleep mode a falling edge at en while txd is low switches the ic into sleep mode. the txd signal has to be logic low during the mode select window ( figure 4-5 on page 10 ). figure 4-4. switch to sleep mode in order to avoid any influence to the lin-pin during switching into sleep mode it is possible to switch the en up to 3.2s earlier to low than the txd. therefore, the best an easiest way are two falling edges at txd and en at the same time. in sleep mode the transmission path is disabled. supply current from v batt is typically i vssleep =10a. the v cc regulator is switched off; nres and rxd are low. the internal slave termi nation between pin lin and pin vs is disabled to minimize the current consumption in case pi n lin is short-circuited to g nd. only a weak pull-up current (typically 10a) between pin lin and pin vs is present. the sleep mode can be activated independently from the current level on pin lin. a voltage less than the lin pre-wake detection v linl at pin lin activates the internal lin receiver and st arts the wake-up detection timer. a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (> t bus ) and a following rising edge at pin lin results in a remote wake-up request. the device switches from sleep mode to fail-safe mode. the v cc regulator is activated, and the inter nal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at rxd and tx d to interrupt the microcontroller ( figure 4-5 on page 10 ). en high can be used to switch directly from sleep/silent to fail-safe mode. if en is still high after vcc ramp up and undervoltage reset time, the ic switches to normal mode. delay time sleep mode t d_sleep = maximum 20s lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en sleep mode normal mode mode select window
ata6629/ata6631 [datasheet] 9165f?auto?10/14 10 figure 4-5. lin wake-up diagram from sleep mode regulator wake-up time off state on state low fail-safe mode normal mode en high microcontroller start-up time delay reset time low low nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus high txd
11 ata6629/ata6631 [datasheet] 9165f?auto?10/14 4.4 sleep or silent mode: behavior at a floating lin-bus or a short circuited lin to gnd in sleep or in silent mode the device has a very low current consumption even during short-circ uits or floating conditions on the bus. a floating bus can arise if the mast er pull-up resistor is missing, e.g., if it is switched off when the lin- master i s in sleep mode or even if the power supply of the master node is switched off. in order to minimize the current consumption i vs in sleep or silent mode during volt age levels at the lin-pin below the lin pre-wake threshold, the receiver is acti vated only for a specific time tmon. if t mon elapses while the voltage at the bus is lower than pre-wake detection low (v linl ) and higher than the lin dominant level, the re ceiver is switched off again and the circuit changes back to sleep respectively silent mode. the current consumption is then i vssleep_short or i vssilent_short (typ. 10a more than i vssleep respectively i vssilent ). if a dominant state is reached on the bus no wake-up will occur. even if the voltage rises above the pre-wake detection high (v linh ), the ic will stay in sleep respectively silent mode (see figure 4-6 on page 11 ). this means the lin-bus must be above the pre-wake detection threshold v linh for a few microseconds before a new lin wake-up is possible. figure 4-6. floating lin-bus during sleep or silent mode if the atmel ? ata6629/ata6631 is in sleep or silent mode and the voltage level at the lin- bus is in dominant state (v lin < v busdom ) for a time period exceeding t mon (during a short circuit at lin, for ex ample), the ic switches back to sleep mode respectively silent mode. the v s current consumption then is i vssleep_short or i vssilent_short (typ. 10a more than i vssleep respectively i vssilent ). after a positive edge at pin lin the ic switches directly to fail-safe mode (see figure 4-7 on page 12 ). i vssleep/silent i vssleep/silent i vsfail v busdom v linl i vs t mon lin pre-wake lin dominant state lin bus mode of operation int. pull-up resistor rlin wake-up detection phase off (disabled) sleep/silent mode sleep/silent mode i vssleep_short / i vssilent_short
ata6629/ata6631 [datasheet] 9165f?auto?10/14 12 figure 4-7. short circuit to gnd on the lin bus during sleep- or silent mode 4.5 fail-safe mode the device automatically switches to fail-safe mode at system power-up. the voltage regulator is switched on (see figure 6-1 on page 15 ). the nres output switches to low for t res = 4ms and gives a reset to the microcontroller. lin communication is switched off. the ic stays in this mode until en is switched to high. the ic then changes to normal mode. a power down of v batt (v s 13 ata6629/ata6631 [datasheet] 9165f?auto?10/14 a wake-up event from either silent or sleep mode will be si gnalled to the microcontroller using the two pins rxd and txd. the coding is shown in table 4-3 . a wake-up event will lead the ic to the fail-safe mode. 4.6 unpowered mode if you connect battery voltage to the application circuit, the vo ltage at the vs pin increases according to the block capacitor (see figure 6-1 on page 15 ). after vs is higher than the vs undervoltage threshold vs th , the ic mode changes from unpowered mode to fail-safe mode. the vcc output voltage reaches its nominal value after t vcc . this time, t vcc , depends on the vcc capacitor and the load. the nres is low for the reset time delay t reset . during this time, t reset , no mode change is possible. if vs drops below vs th , then the ic switches to unpowered mode. t he behaviour of vcc, nres and lin is shown in figure 4-8 . figure 4-8. vcc versus vs for the vcc = 3.3v regulator table 4-3. signalling fail-safe sources fail-safe sources txd rxd lin wake up (pin lin) low low vs th (battery) undervoltage detection high low vcc lin nres vs regulator drop voltage v d 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v s in v 5.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in v
ata6629/ata6631 [datasheet] 9165f?auto?10/14 14 5. fail-safe features during a short-circuit at lin to v battery , the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff and the lin output is switched off. the ch ip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high because lin is high. during lin overtemperature switch-off, the v cc regulator is working independently. during a short-circuit from lin to gnd the ic can be switc hed into sleep or silent mode and even in this case the current consumption is lower than 30a in sleep mode and lower than 70a in silent mode. if the short-circuit disappears, the ic starts with a remote wake-up. sleep or silent mode: during a floating condition on the bus the ic switches back to sleep mode/silent mode automatically and thereby the current consumption is lower than 30a/70a. the reverse current is < 2a at pin lin during loss of v batt . this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. during a short circuit at vcc, the ou tput limits the output current to i vcclim . because of undervoltage, nres switches to low and sends a reset to the microcontroller. the ic swit ches into fail-safe mode. if the chip temperature exceeds the value t vccoff , the v cc output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of fail-safe mode, the v cc voltage will switch on again although en is switched off from the microcontroller.the microcontroller can then start with normal operation. pin en provides a pull-down resistor to force the tr ansceiver into recessive m ode if en is disconnected. pin rxd is set floating if v batt is disconnected. pin txd provides a pull-up resistor to force the transce iver into recessive mode if txd is disconnected. after switching the ic into normal mode the txd pin must be pulled to high longer than 10s in order to activate the lin driver. this feature prevents the bu s from being driven into dominant state when the ic is switched into normal mode and txd is low. if txd is short-circuited to gnd, it is possible to switch to sleep mode via enable after t > tdom.
15 ata6629/ata6631 [datasheet] 9165f?auto?10/14 6. voltage regulator figure 6-1. v cc voltage regulator: ramp up and undervoltage the voltage regulator needs an external capacitor for compensation and to smooth t he disturbances from the microcontroller. it is recommended to use an electrolytic c apacitor with c > 1.8f and a ceramic capacitor with c = 100nf. the values of these capacitors can be vari ed by the customer, depending on the application. with this special so8 package (fused lead frame to pin 3) an r thja of 80k/w is achieved. therefore, it is recommended to con nect pin 3 with a wide gnd plate on the printed board to get a good heat sink. the main power dissipation of the ic is created from the v cc output current i vcc , which is needed for the application. figure 6-2 shows the safe operating area of the atmel ? ata6631. figure 6-2. power dissipation: safe operating area: v cc output current versus supply voltage v s at different ambient temperatures due to r thja = 80k/w for programming purposes of the microcontroller, it is potentionally necessary to supply the v cc output via an external power supply while the v s pin of the system basis chip is disconnected. th is will not affect the system basis chip. nres 5v/3.3v vcc vs 5v/3.3v v thun t res_f t reset t vcc 5.5v/3.8v 12v 56789101112131415161718 tamb = 85c tamb = 95c tamb = 105c tamb = 115c v s (v) 90 80 70 60 50 40 30 20 10 0 i vcc (ma)
ata6629/ata6631 [datasheet] 9165f?auto?10/14 16 7. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500ms t a =25c output current i vcc 85ma v s +40 v pulse time 2min t a =25c output current i vcc 85ma v s 27 v logic pins (rxd, txd, en, nres) ?0.3 +5.5 v output current nres i nres +2 ma lin - dc voltage ?27 +40 v v cc - dc voltage ?0.3 +5.5 v esd according to ibee lin emc test specification 1.0 following iec 61000-4-2 - pin vs, lin to gnd 8 kv esd hbm following stm5.1 with 1.5 k /100 pf - pin vs, lin to gnd 6 kv hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) 3 kv cdm esd stm 5.3.1 750 v machine model esd aec-q100-revf(003) 200 v junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c 8. thermal characteristics parameters symbol min. typ. max. unit thermal resistance junction to ambient (free air) r thja 145 k/w special heat sink at gnd (pin 3) on pcb r thja 80 k/w thermal shutdown of v cc regulator t vccoff 150 160 170 c thermal shutdown of lin output t linoff 150 160 170 c thermal shutdown hysteresis t hys 10 c
17 ata6629/ata6631 [datasheet] 9165f?auto?10/14 9. electrical characteristics 5v < v s < 27v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 5 13.5 27 v a 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v vs i vssleep 2 10 14 a a sleep mode, v lin = 0v bus shorted to gnd v s < 14v vs i vssleep_short 3 20 30 a a 1.3 supply current in silent mode bus recessive v s < 14v without load at vcc vs i vssilent 20 35 50 a a silent mode v s < 14v bus shorted to gnd without load at vcc vs i vssilent_short 25 45 70 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vcc vs i vsrec 0.3 0.8 ma a 1.5 supply current in normal mode bus dominant v s < 14v v cc load current 50ma vs i vsdom 50 53 ma a 1.6 supply current in fail-safe mode bus recessive v s < 14v without load at vcc vs i vsfail 0.35 0.53 ma a 1.7 vs undervoltage threshold switch to unpowered mode vs v sthu 3.7 4.2 4.7 v a switch to fail-safe mode vs v sthf 4.0 4.5 5 v a 1.8 vs undervoltage hysteresis vs v sth_hys 0.3 v a 2 rxd output pin 2.1 low level output sink current normal mode v lin =0v, v rxd =0.4v rxd i rxd 1.3 2.5 8 ma a 2.2 low level output voltage i rxd = 1ma rxd v rxdl 0.4 v a 2.3 internal resistor to v cc rxd r rxd 3 5 7 k a 3 txd input/output pin 3.1 low level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high level voltage input txd v txdh 2 v cc + 0.3v v a 3.3 pull-up resistor v txd =0v txd r txd 125 250 400 k a 3.4 high level leakage current v txd =v cc txd i txd ?3 +3 a a 3.5 low level output sink current at local wake-up request fail-safe mode v lin = v s v wake = 0v v txd = 0.4v txd i txdwake 2 2.5 8 ma a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata6629/ata6631 [datasheet] 9165f?auto?10/14 18 4 en input pin 4.1 low level voltage input en v enl ?0.3 +0.8 v a 4.2 high level voltage input en v enh 2 v cc + 0.3v v a 4.3 pull-down resistor v en = vcc en r en 50 125 200 k a 4.4 low level input current v en = 0v en i en ?3 +3 a a 5 nres open drain output pin 5.1 low level output voltage v s 5.5v i nres =1ma nres v nresl 0.14 v a 5.2 low level output low 10 k to 5v v cc =0v nres v nresll 0.2 v a 5.3 undervoltage reset time v vs 5.5v c nres = 20pf nres t reset 2 4 6 ms a 5.4 reset debounce time for falling edge v vs 5.5v c nres = 20pf nres t res_f 1.5 10 s a 5.5 switch off leakage current v nres = 5.5v nres ?3 +3 a a 6 vcc voltage regulator atmel ata6629 6.1 output voltage vcc 4v < v s < 18v (0ma to 50ma) vcc vcc nor 3.234 3.366 v a 4.5v < v s < 18v (0ma to 85ma) vcc vcc nor 3.234 3.366 v c 6.2 output voltage v cc at low v s 3v < vs < 4v vcc vcc low v vs ? v drop 3.366 v a 6.3 regulator drop voltage vs > 3v, i vcc = ?15ma vcc v d1 200 mv a 6.4 regulator drop voltage vs > 3v, i vcc = ?50ma vcc v d2 500 700 mv a 6.5 line regulation maximum 4v < vs < 18v vcc vcc line 0.1 0.2 % a 6.6 load regulation maximum 5 ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 6.7 power supply ripple rejection 10 hz to 100khz c vcc = 10f vs = 14v, i vcc = ?15ma 50 db d 6.8 output current limitation vs > 4v vcc i vccs ?240 ?160 ?85 ma a 6.9 external load capacity 0.2 < esr < 5 at 100khz for phase margin 60 vcc c load 1.8 10 f d esr < 0.2 at 100khz for phase margin 30 6.10 vcc undervoltage threshold referred to vcc vs > 4v vcc v thunn 2.8 3.2 v a 6.11 hysteresis of undervoltage threshold referred to vcc vs > 4v vcc vhys thun 150 mv a 6.12 ramp up time vs > 4v to vcc = 3.3v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 320 500 s a 9. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
19 ata6629/ata6631 [datasheet] 9165f?auto?10/14 7 vcc voltage regulator atmel ata6631 7.1 output voltage vcc 5.5v < v s < 18v (0ma to 50ma) vcc vcc nor 4.9 5.1 v a 6v < v s < 18v (0ma to 85ma) vcc vcc nor 4.9 5.1 v c 7.2 output voltage v cc at low v s 4v < vs < 5.5v vcc vcc low v vs ? v d 5.1 v a 7.3 regulator drop voltage vs > 4v, i vcc = ?20ma vcc v d1 250 mv a 7.4 regulator drop voltage vs > 4v, i vcc = ?50ma vcc v d2 400 600 mv a 7.5 regulator drop voltage vs > 3.3v, i vcc = ?15ma vcc v d3 200 mv a 7.6 line regulation maximum 5.5v < vs < 18v vcc vcc line 0.1 0.2 % a 7.7 load regulation maximum 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 7.8 power supply ripple rejection 10hz to 100khz c vcc = 10f vs = 14v, i vcc = ?15ma 50 db d 7.9 output current limitation vs > 5.5v vcc i vccs ?240 ?160 ?85 ma a 7.10 external load capacity 0.2 < esr < 5 at 100khz for phase margin 60 vcc c load 1.8 10 f d esr < 0.2 at 100khz for phase margin 30 7.11 vcc undervoltage threshold referred to vcc vs > 5.5v vcc v thunn 4.2 4.8 v a 7.12 hysteresis of undervoltage threshold referred to vcc vs > 5.5v vcc vhys thun 250 mv a 7.13 ramp up time vs > 5.5v to vcc = 5v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 320 500 s a 8 lin bus driver: bus load conditions: load 1 (small): 1nf, 1k ; load 2 (large): 10nf, 500 ; internal pull-up rrxd = 5k ; crxd = 20pf, load 3 (medium): 6.8nf, 660 characterized on samples 10.7 and 10.8 specifies the timing parameters for proper operation at 20kbit/s and 10.9 and 10.10 at 10.4kbit/s 8.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s v a 8.2 driver dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 8.3 driver dominant voltage v vs = 18v r load = 500 lin v _hisup 2 v a 8.4 driver dominant voltage v vs = 7v r load = 1000 lin v _losup_1k 0.6 v a 8.5 driver dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 8.6 pull?up resistor to v s the serial diode is mandatory lin r lin 20 30 47 k a 9. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata6629/ata6631 [datasheet] 9165f?auto?10/14 20 8.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode = 10ma lin v serdiode 0.4 1.0 v d 8.8 lin current limitation v bus = v batt_max lin i bus_lim 40 120 200 ma a 8.9 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v batt = 12v lin i bus_pas_dom ?1 ?0.35 ma a 8.10 leakage current lin recessive driver off 8v < v batt < 18v 8v < v bus < 18v v bus v batt lin i bus_pas_rec 10 20 a a 8.11 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network gnd device = v s v batt = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 8.12 leakage current at disconnected battery. node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v batt disconnected v sup_device = gnd 0v < v bus < 18v lin i bus_no_bat 0.1 2 a a 8.13 capacitance on pin lin to gnd lin c lin 20 pf d 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s v a 9.2 receiver dominant state v en = 5v lin v busdom ?27 0.4 v s v a 9.3 receiver recessive state v en = 5v lin v busrec 0.6 v s 40 v a 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 x v s 0.175 v s v a 9.5 pre-wake detection lin high level input voltage lin v linh v s ? 2v v s + 0.3v v a 9.6 pre-wake detection lin low level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v v a 10 internal timers 10.1 dominant time for wake? up via lin bus v lin = 0v lin t bus 30 90 150 s a 10.2 time delay for mode change from fail-safe into normal mode via pin en v en = 5v en t norm 5 15 20 s a 9. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
21 ata6629/ata6631 [datasheet] 9165f?auto?10/14 10.3 time delay for mode change from normal mode to sleep mode via pin en v en = 0v en t sleep 8 16 25 s a 10.4 txd dominant time out time v txd = 0v txd t dom 27 55 70 ms a 10.5 time delay for mode change from silent mode into normal mode via en v en = 5v en t s_n 5 15 40 s a 10.6 monitoring time for wake- up over lin bus lin t mon 6 10 15 ms a 10.7 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 a 10.8 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 a 10.9 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 a 10.10 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 a 10.11 slope time falling and rising edge at lin v s = 7.0v to 18v lin t slope_fall t slope_rise 3.5 22.5 s a 11 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions: internal pull-up; crxd = 20pf 11.1 propagation delay of receiver figure 9-1 on page 22 v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) rxd t rx_pd 6 s a 11.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 9. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata6629/ata6631 [datasheet] 9165f?auto?10/14 22 figure 9-1. definition of bus timing characteristics txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
23 ata6629/ata6631 [datasheet] 9165f?auto?10/14 figure 9-2. application circuit 3 gnd 2 en 6 txd 5 rxd vcc + 100nf 100nf 220pf 10k 10f 22f 8 nres 7 short circuit and overtemperature protection normal/silent/ fail-safe mode 3.3v/5v control unit normal and fail-safe mode rf filter vcc micro- controller lin vs lin-bus 1 4 txd time-out timer slew rate control undervoltage reset sleep mode vcc switched off wake-up bus timer atmel ata6629/31 receiver v cc v bat - + v cc 5k gnd 1k
ata6629/ata6631 [datasheet] 9165f?auto?10/14 24 11. package information 10. ordering information extended type number package remarks ata6629-gaqw so8 3.3v lin system basis chip, pb -free, 4k, taped and reeled ata6631-gaqw so8 5v lin system basis chip, pb -free, 4k, taped and reeled package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5185.01-4 1 05/08/14 package: so8 common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.15 0.25 0.1 a1 3.9 4 3.8 e1 0.4 0.5 0.3 b 1.27 bsc e 0.2 0.25 0.15 c 0.65 0.9 0.4 l 66.2 5.8 e 4.9 5 4.8 d 1.47 1.55 1.4 a2 1.65 1.8 1.5 a 85 14 d b e a a1 a2 c e1 e l pin 1 identity
25 ata6629/ata6631 [datasheet] 9165f?auto?10/14 12. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9165f-auto-10/14 ? put datasheet in the latest template ? section 10 ?ordering information? on page 24 updated ? section 11 ?package information? on page 25 updated 9165e-auto-04/14 ? put datasheet in the latest template 9165d-auto-03/11 ? features on page 1 changed ? section 1 ?description? on pages 1 to 2 changed ? section 3 ?functional description? on pages 3 to 4 changed ? section 4 ?modes of operation? on pages 5 to 12 changed ? section 5 ?fail-safe features? on page 13 changed ? section 6 ?voltage regulator? on pages 14 to 15 changed ? section 7 ?absolute maximum ratings? on page 16 changed ? section 9 ?electrical characteristics? on pages 17 to 23 changed 9165c-auto-10/10 ? section 9 ?electrical characteristics? num bers 1.7 on page 17 and 10.3 on page 20 changed 9165b-auto-05/10 ? features on page 1 changed ? text under heading 3.3 changed ? text under heading 4.2 changed ? abs.max.rat.table -> values in row ?esd hbm following....? changed ? el.char.table -> rows changed: 1.2, 1.3, 5.1, 5.2, 6.5, 6.6, 6.7, 6.8, 6.12, 7.6, 7.7, 7.8, 7.9, 7.13 ? el.char.table -> row 8.13 added
x x xx x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: 9165f?auto?10/14 atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in c onnection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability wh atsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, pu nitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information ) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atme l products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaim er: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by atmel as automotive-grade.

▲Up To Search▲

Price & Availability of ATA6631-14

	To Download ATA6631-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .